I’ve been extremely busy the last 10 weeks. I decided it would be a good idea to take 4 graduate level computer engineering classes (3 project-based) at the same time. Guess what – it’s not. But, I made it through and I’m pretty damn proud of myself. So, since I think it’s pretty interesting, I decided to post what I’ve been up to the past couple of months.

First, the most recently completed project – VLSI. For my project, my partner and I had to design and layout an 8-bit Brent-Kung adder with BIST using TSMC 0.35 micron N-Well process technology. What’s that? Well, an 8-bit adder is a device that adds two 8-bit numbers. Brent-Kung is a specific type of tree-adder (defining the way the circuit is organized) that is used as a basis for many other tree-adder networks as it attempts to minimize wiring tracks and fanout gate count. BIST stands for built-in self test, a mechanism that allows the circuit to test itself. The final area for the entire circuit (8-bit BK adder with BIST) was 28,757 square microns. Any one extra interested in this can read my final report. For fun, and to show how one goes about doing physical layout, here’s some pictures of our final layout. First, the adder with BIST. On the left is the adder/BIST on the I/O pad. On the right, the adder/BIST itself. For a closer view, just click on the image.

Next,the adder layout. Note: that space at the left top and bottom was on purpose: it’s for the DFF.

Next, everyone’s favorite ASCII art: the “I passed LVS check mark/smiley face.” For those not-so-familiar with VLSI/Mentor Graphics tools, LVS stand for layout versus schematic. That means it compares my wonderful layout (those colorful polygons seen above) versus my schematic to ensure the extracted netlists from both the layout and schematic match. The schematic is functionally verified to work correctly by simulating it. In theory, if the schematic works and the layout passes LVS, the circuit should work. However, post-layout simulations should be done as well.

When we finished the layout, we printed it to the 36″ plotter. Naturally, I hung my masterpiece on the wall above my bed.

The next project of interest: the heart rate monitor. The point of the project was to implement a complete automatic data acquisition system. (sensors, signal conditioning, analog-to-digital conversion, uController, and finally digital-to-analog conversion). The sensor for the system that we used was an opto-isolator. It works by emitting IR light through an LED that is then picked up by a photo transistor. So, for the heart rate sensor, a human finger rests on top of the opto-isolator that produces a varying voltage as a result of the blood flow through the finger. This signal is quite noisy and quite low in amplitude, so it was connected to an amplifier and low pass filter. Because the ATD we used requires 0 to 5V on the input, we added a final stage to level shift and amplify the signal to that range. This was then connected to the input of an HCS12 microcontroller programmed to calculate the heart rate and display it to a monitor via serial connection. If you’re interested, we made a poster displaying the schematics and a bit more detail on how the system works. You can take a look at that here. Here’s a picture of the final circuit and my beautiful finger.

And, just to prove it works, here’s the oscilloscope output.

The final project I’ve been working on is an implementation of a median filter on a FPGA. Median filters are used to remove salt and peppering effects from an image. The system interfaces an external memory chip to the FPGA and connects to a PC via a parallel port. A program from a computer sends the gray-scale PNG image to the FPGA. The FPGA then processes the image and sends it back to the PC. The project was done using VHDL and the FPGA was a Xilinx Spartan II. In addition, a histogram stretching algorithm was implemented on the FPGA. Histogram stretching is a form of contrast enhancement. Once the median filter was successfully implemented, the histogram stretching algorithm was quite easy. Unfortunately, there’s no pictures for this one. This was a long quarter, but now I get 2 weeks to relax and work on a couple of my independent projects before I dive back into the school work.